This invention relates to methods and apparatus for electrical testing of printed circuit boards and more particularly to functional testing of high-speed digital printed circuit boards.
The availability of high performance modular digital test instrumentation suggests such equipment could be applied in non-traditional applications, such as printed circuit board (PCB) test. The use of digital pattern generators to provide input stimulus to the unit under test (UUT) and digital analysis units (logic analyzers) to obtain and verify the responses of the UUT permits a low cost, modular, high performance means of testing PCB functionality to be realized.
This approach is well suited to verifying the functional operation of the UUT by examining the output signals generated by the PCB. Controlled-impedance wiring (twisted pair or shielded cable) can be used to deliver the signals from the pattern generator to the UUT card-edge connector; use of terminating resistors there can insure proper delivery of high speed stimulus. Signal probes of the logic analyzer can be connected directly to the card-edge connector; the high-impedance analyzer inputs are physically only a short distance from the signal sources on the PCB. The high speed signal behavior of the UUT can readily be monitored by the logic analyzer.
A drawback of this approach, commonly referred to as "functional testing," is that while determination of whether the UUT is properly functional or not may be made, determination of the cause of failure may be quite difficult. A superior approach would employ a bed-of-nails (BON) to allow access to the internal nodes of the PCB. While still applying stimulus to the UUT inputs, more comprehensive testing could be carried out by observing the behavior of any and all device signals on the PCB. Verification of pass/fail functionality could still be made, and determination of exactly which device output(s) first behaved in an other-than-expected fashion, at exactly which point in the stimulus sequence, becomes possible.
Determination of pass/fail functionality is made through comparison of the UUT behavior against a reference. This reference may be taken from the output of a logic simulation program (such as could be run on a computer-aided engineering (CAE) workstation). Alternatively, the actual behavior (not simulated) of a known-good PCB in response to the pattern generator stimulus could be recorded by the logic analyzer and the information stored for future comparison use.
Unfortunately, two problems prevent the efficient application of test instrumentation to PCB functional test using BON fixturing. The first has to do with the electrical characteristics of the fixture. Conventionally, the wiring in the BON fixture (connecting the spring-loaded probes, which press against the PCB nodes, to connectors on the back or bottom of the fixture) is composed of many individual unshielded runs, each possibly several feet in length. Signals, especially if they are high speed, are thus subject to crosstalk and noise. The electrical environment is unpredictable since the wiring impedance is not controlled. Furthermore, the effects of the wiring on the electrical behavior of the signals is significant, especially in high speed situations. Ringing and reflections cause the waveforms seen by the logic analyzer to no longer resemble the actual UUT circuit node behavior. Dynamic loading of the PCB circuit nodes by the fixture wiring alters the electrical behavior of the UUT nodes compared with their behavior when not on the BON.
This problem can be solved by building a testing system which has been specially engineered to keep the electrical distance of the test electronics from the UUT very short. This approach, employed by high-end "combinational" testers, uses wire lengths within the BON fixture of less than six inches. UUT loading and signal ringing and reflections are all thereby reduced to acceptable levels. The price of such a system is high because of the significant development expense involved; the special short-wire fixtures required are also relatively expensive.
An alternative solution is to place active buffering at each UUT node within the BON fixture. The buffers reduce loading on the UUT nodes and are able to drive terminated controlled-impedance lines of significant length. This approach is economically unfeasible due to the number of buffers required for a typical-size PCB, especially in view of the fact that each board type to be tested requires its own fixture.
The second problem comes from the recognition that PCB's may have up to thousands of nodes which need to be monitored, while logic analyzers usually have no more than one hundred signal inputs. Even the highest-end analysis units, such as Jektronix model DAS9200, are expandable to no more than five hundred inputs, typically at significant expense.
Without economic solution of these problems, BON-based high performance digital functional testing employing modular digital test instrumentation remains impracticable. Accordingly, a need remains for an improved way to functionally test high-speed, multi-node digital printed circuit boards.